High Performance and Capacity Mixed HDL Simulation - ModelSim
Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
ModelSim Recommends
New Academy Modules
The Advanced UVM module consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM module to take your UVM understanding to the next level.
Learn more about Advanced UVM.
The UVM Express module is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. If you don't have a full-time verification expert on staff, or if you are not a full-time verification engineer, the UVM Express module's 3 sessions might be for you.
Learn more about UVM Express.
Featured Event
ModelSim - Improve Simulation Runtime and Debug
This comprehensive technical seminar will help get you started using traditional RTL debug features such as debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files and VCD stimulus.
View this, archived web seminar.
* Registration is fulfilled on Mentor.com