Using ModelSim to Improve Simulation Runtime and Debug Productivity

In this webinar, you’ll discover how to significantly reduce simulation runtime and improve debug productivity using ModelSim from Mentor Graphics.

ModelSim’s integrated HDL support helps you reduce SoC design and verification time, tasks which typically consume as much as 70 percent of total development time. This comprehensive technical seminar will help get you started using traditional RTL debug features such as debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files and VCD stimulus.

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ModelSim DE: Xilinx SecureIP Support, Assertions with SystemVerilog and PSL plus more

You already know that ModelSim is the simulator of choice for leading electronics companies in all industries. In addtion to native compile, single kernel simulation technology, an intuitive, easy-to-use GUI, integrated project management, source code templates and wizards, we now offer support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support. The seminar will review these features and capabilities now available.

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Using Code Coverage with ModelSim

With today's complex SoCs, the time spent on verification now consumes 70 percent of the total development time. A more efficient and effective verification methodology is crucial for improving first pass silicon success. Gathering and measuring coverage statistics are a critical part of this methodology. Coverage metrics are needed to assess the extent and quality of verification functionality, interface behaviors and corner cases for RTL structures. These metrics allow you to focus on actionable portions of the design. This session will discuss how to perform an easy measurement techniques with ModelSim that gets you well on your way toward 100% Coverage.

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