Compare the ModelSim Product Line
ModelSim Product and Feature Comparison
is available in .pdf
| Feature | ModelSim PE | ModelSim DE | ModelSim SE |
| Block/Small System Simulation, Windows |
Block/Small System Simulation, Windows/Linux |
Large Block/System Simulation, All Platforms |
|
| General | |||
| Licensing - Floating License |
Option | Option | Y |
| Language Neutral License |
Option | ||
| ASIC Sign-Off | Y | ||
| HDL Editor | Y | Y | Y |
| Integrated Project Manager |
Y | Y | Y |
| Source Code Templates and Wizards |
Y | Y | Y |
| Platform-Independent Compiled Database |
Y | Y | Y |
| Native-Compiled Architecture |
Y | Y | Y |
| Incremental Compilation |
Y | Y | Y |
| 32/64-Bit Cross-Compatability |
Y | ||
| Languages | |||
| VHDL | Y | Y | Y |
| Verilog | Y | Y | Y |
| VHDL Plus Verilog Dual Language |
Option | Option | Option |
| Verilog 2001, 2005 |
Y | Y | Y |
| SystemVerilog Design |
Y | Y | Y |
| SystemVerilog and PSL IEEE 1850 Assertions |
Y | ||
| SystemC 2.2 | Option | Option | Option |
| Analog/Mixed Signal (Questa AMS Product) |
Option | ||
| Verilog PLI/VPI |
Y | Y | Y |
| SystemVerilog Direct Programming Interface |
Y | Y | Y |
| VHDL FLI | Y | ||
| Debug | |||
| Interactive Debug |
Y | Y | Y |
| Post-Simulation Debug |
Y | ||
| Enhanced Dataflow Window |
Option | Y | Y |
| Source Annotation |
Option1 | Y | Y |
| Hyperlinked Navigation |
Y | Y | Y |
| Assertion Thread Debug |
Y | ||
| Advanced FSM Debug |
Y | ||
| C Debugger | Option2 | Option2 | Y |
| Memory Window | Y | Y | Y |
| Extra Standalone Viewer |
Option | Option | Option |
| Multiple Waveform Windows |
Y | ||
| Waveform Compare |
Option | Y | Y |
| Transaction Viewing (SystemC) |
Option2 | Option2 | Option2 |
| JobSpy | Y | ||
| SignalSpy | Y | Y | Y |
| User-Customizable GUI (via Tk) |
Y | ||
| Cross Referencing between Windows |
Y | Y | Y |
| Coverage | |||
| Code Coverage (with Toggle Coverage) |
Option | x | x |
| Unified Coverage DataBase (UCDB) |
Y4 | Y | Y |
| Coverage Viewer |
Y4 | Y | Y |
| Test Ranking | Y4 | Y | Y |
| HTML Reporting | Y4 | Y | Y |
| Simulation | |||
| Single-Kernel Simulation Engine |
Y | Y | Y |
| Verilog RTL & Gate Performance Optimizations |
Y | ||
| VHDL RTL & VITAL Performance Optimizations |
Y | ||
| Performance and Memory Profiler |
Option | Option | Y |
| Separate Elaboration |
Y | ||
| Waveform Management Tool Set |
Y | Y | Y |
| VCD and Extended VCD Support |
Y | Y | Y |
| VCD Re-Simulation |
Y | Y | Y |
| Batch Mode Simulation |
Y | Y | Y |
| Integrated Sim Farm Support (via JobSpy) |
Y | ||
| Interactive Simulation |
Y | Y | Y |
| Black Box Regression Suite Throughput |
Y | ||
| Checkpoint & Restore |
Y | ||
| VHDL 2008 Encryption |
Y | Y | Y |
| Verilog 2005 Encryption |
Y | Y | Y |
| SWIFT Interface / SmartModels |
Option | Option | Y |
| SecureIP | Option3 | Y | Y |
| Synopsys Hardware Modeler Support |
Y | ||
| Platform Support |
|||
| 32-Bit OS Support |
Windows XP/Vista | Windows XP/Vista/Linux |
Linux, Solaris, Windows XP/Vista |
| 64-Bit OS Support |
Linux x86-64, Solaris 64 |
1 - Included in Enhanced Dataflow Option
2 - Included in SystemC Option
3 - Option for use with VHDL
4 - Data generated with code coverage option