High Performance and Capacity Mixed HDL Simulation - ModelSim
Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
ModelSim Recommends
New Release - ModelSim 10.1
The latest version of ModelSim is now available for download. Learn more.
Featured Event
ModelSim - Improve Simulation Runtime and Debug
This comprehensive technical seminar will help get you started using traditional RTL debug features such as debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files and VCD stimulus.
View this, archived web seminar.
* Registration is fulfilled on Mentor.com
