High Performance and Capacity Mixed HDL Simulation - ModelSim
Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
Verification Academy Course
Power Aware Verification
Join Subject Matter Experts; Erich Marschner and Chuck Seeley for a new course on Power Aware Verification and the UPF.
View the first five Power Aware Verification sessions, the latest addition to the Verification Academy video library.
